1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a program method thereof, and more particularly, to a non-volatile memory device that may reduce a program unit time and a program method thereof.
2. Description of the Related Art
Memory devices are divided into volatile memory devices and non-volatile memory devices according to whether data are retained when a power supply is cut off. Volatile memory devices are memory devices which lose the data stored therein when a power supply is cut off. Examples of the volatile memory devices include Dynamic Random Access Memory (DRAM) devices and Synchronous DRAM (SDRAM). On the other hand, non-volatile memory devices retain the data stored therein even if a power supply is cut off. Examples of the non-volatile memory devices include a flash memory device.
The non-volatile memory devices may electrically program and erase data and there are increasing demands for non-volatile memory devices which do not have to perform a refresh operation where a data is reprogrammed at a predetermined cycle. Here, a program operation is an operation of writing a data in a memory cell.
A NAND flash memory which forms a string, where a plurality of memory cells (that is, a structure where adjacent cells share a drain or source with another) are coupled in series, has been developed to highly integrate a memory device. A NAND flash memory device is a memory that sequentially reads data, which is different from a NOR flash memory.
As a demand for NAND flash memory devices as data storage media increases, large-volume flash memory devices are useful. To increase the storage capacity in a small chip size, a multi-level cell (MLC) structure where a data of more than 2 bits is stored in one memory cell is used. The MLC technology is effective in increasing the data storage capacity without much change in the fabrication technology. In other words, differently from a single level cell (SLC) structure, the MLC structure has a program cell threshold voltage distribution, where the MLC structure may represent data of two bits, three bits, four bits or more.
For NAND flash memory devices of the SLC or MLC structure, a programming speed and a decrease in the distribution width of cell threshold voltages Vt are significant. Particularly, since it is expected that the MLC technology advance into 8 level technology, the decrease in the distribution width of cell threshold voltages Vt of memory cells is desired. Therefore, a program method using Incremental Step Pulse Program (ISPP) method in which a selected page is programmed several times by gradually increasing the bias voltage applied to a word line on the basis of a predetermined step bias increase unit is developed and implemented.
Hereafter, with reference to FIG. 7, a structure of a conventional non-volatile memory device is briefly described. FIG. 7 illustrates a memory cell array of the conventional non-volatile memory device.
Referring to FIG. 7, the memory cell array includes a plurality of cell strings coupled with bit lines BL0 to BLN, and each cell string includes a source selection transistor SST, a plurality of memory cell transistors MC0 to MC31, and a drain selection transistor DST.
A gate of the source selection transistor SST is coupled in common with the source selection lines SSL. A gate of the drain selection transistor DST is coupled with a drain selection line DSL. The control gates of the memory cell transistors MC0 to MC31 are coupled with word lines WL0 to WL31. The memory cell transistors MC0 to MC31 are coupled in series between the source selection transistor SST and the drain selection transistor DST.
The number of memory cells included in one cell string may be 32, as illustrated in the drawing, or may be different according to the storage capacity of a memory device. The source selection transistor SST and the drain selection transistor DST are typical MOS transistors, and the memory cell transistors MC0 to MC31 are floating gate transistors.
In the memory device of the above-described structure, the physical characteristics of the memory cell transistors MC0 to MC31 may differ according to the position of the memory cell transistors MC0 to MC31 disposed in a cell string.
To address such a feature, a program verification bias voltage may be adjusted appropriately to the physical characteristics of the memory cell transistors MC0 to MC31 based on the positions of the memory cell transistors MC0 to MC31. To this end, a program verification bias voltage level is to be calculated every time when the program verification bias voltage is to be used.
Here, the program verification bias voltage includes a characteristic voltage according to the characteristics of each memory cell and a default bias voltage, e.g., approximately 5V or lower. The characteristic voltage includes an offset bias voltage for each group, e.g., a voltage of approximately 3V or lower, and an offset bias voltage of an edge word line, e.g., a voltage of approximately 3V or lower. Here, the program unit time is a time ranging from a moment when a program pulse is applied to a moment when a plurality of program verification bias voltages are applied.
FIG. 8 is a waveform diagram showing application of a program pulse and a program verification bias voltage for a conventional memory cell array (for example, the memory array shown in FIG. 7). More specifically, as illustrated in FIG. 8, after the program pulse is applied, a calculation operation for generating a first program verification bias voltage PV1 is performed for a first setup duration P1D, and the first program verification bias voltage PV1 generated as a calculation operation result is applied to the word line of a corresponding memory cell. The above calculation operation is performed by summing the default bias voltage, the offset bias voltage for each group, and the offset bias voltage of an edge word line.
Subsequently, a calculation operation for generating a second program verification bias voltage PV2 is performed for a second setup duration P2D, and the second program verification bias voltage PV2 generated as a result of the calculation operation is applied to the word line of a corresponding memory cell.
Subsequently, a calculation operation for generating a third program verification bias voltage PV3 is performed for a third setup duration P3D, and the third program verification bias voltage PV3 generated as a result of the calculation operation is applied to the word line of a corresponding memory cell.
Subsequently, a calculation operation for generating a fourth program verification bias voltage PV4 is performed for a fourth setup duration P4D, and the fourth program verification bias voltage PV4 generated as a result of the calculation operation is applied to the word line of a corresponding memory cell.
Here, if the program verification bias voltage level is calculated whenever the program verification bias voltage is used, the program unit time increases.
Particularly, since the application of the program pulse and the application of the program verification bias voltage according to the program operation are performed iteratively, the resulting increase in the program unit time as described above delays the program operation.